1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit having a frequency limiting function.
2. Description of the Related Art
FIG. 4 shows a block diagram a configuration of conventional PLL circuit having a frequency limiting function, and FIG. 5 shows a relation between phase difference detected by phase comparator and output frequency of voltage control oscillator (VCO). As shown in FIG. 4, a phase comparator (PC) 1 compares a phase of a synchronizing-source reference clock (REFCLK) signal F21 and a phase of a signal F22 to each other to then output a phase difference signal P20 indicating a phase difference between these signals F21 and F22. A phase watcher (P-WATCH) 2 activates only a signal S21 if the phase difference indicated by the phase difference signal P20 is not higher than a value a shown in FIG. 5 and activates only a signal S22 if that phase difference is a value b or higher.
A SEL 3 receives the incoming phase difference signal P20, a signal indicating the phase difference a, and a signal indicating the phase difference b. The SEL 3 selects the phase difference signal P20 input from the PC 1 to output it as the difference signal P21 if neither of the signals S21 and S22 is active. On the other hand, if the signal S21 is active, the SEL 3 selects the signal indicating the phase difference a to output it as the phase difference signal P21 and, if the signal S22 is active, selects the signal indicating the phase difference b to output it as the phase difference signal P21.
A P-VCONV 4 converts the phase difference signal P21 output from the SEL 3 into a VCO control voltage signal V21. An LPF 5 integrates the VCO control voltage signal V21 output from the P-VCONV 4 to convert it into a VCO frequency-controlled voltage signal V22. A VCO 6 outputs a VCO output clock (VCOCLK) signal F20 having a frequency proportional to a control voltage indicated by the VCO frequency-controlled voltage signal V22. A CTR 7 outputs a signal F22 obtained by dividing the frequency of the VCOCLK signal F20. Thus, in the conventional PLL circuit, the frequency of the VCOCLK signal F20 is limited in a range between a predetermined upper limit c and a predetermined lower limit d, both inclusive.
In the conventional PLL circuit, however, if the REFCLK signal F21 is input which has a frequency outside the synchronization-enabled range (that is, a frequency higher than the value c or lower than the value d in FIG. 5), a phase slip occurs in that the phase difference (indicated by the phase difference signal P20) between the signals F21 and F22 rapidly changes from the value e to the value f or vice versa, thus resulting in a problem of such periodical changing of the VCO output frequency as shown in FIG. 6.